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HPPAC 2011
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HPPAC 2009
HPPAC 2008
HPPAC 2007
HPPAC 2006

HPPAC 2005


Important Dates

 

Paper submission:
20th January 2012 (extended) at 11:59PM EST Author notification:
6th February 2011


Camera-ready due:
21st February 2011


Shanghai, China

The Eighth Workshop on
High-Performance, Power-Aware Computing

May
21, 2012, Shanghai, China

 
 
 

The 8th Workshop on High-Performance, Power-Aware Computing (HPPAC 2012) will be held on May the 21st, 2012 in Shanghai, China, in conjunction with the 26th Annual International Parallel & Distributed Processing Symposium (IPDPS 2012), to be held on May 21-25, 2012, Shanghai, China.

Scope

High-performance computing is and has always been performance-oriented. However, a consequence of the push towards maximum performance is increased energy consumption, especially in datacenters and supercomputing centers. Moreover, as peak performance is rarely attained, some of this energy consumption results in little or no performance gain. In addition, large energy consumption costs datacenters and supercomputing centers a significant amount of money and wastes natural resources.

The main goal of this workshop is to provide a timely forum for the exchange and dissemination of new ideas, techniques, and research in high-performance, power-aware computing (HPPAC). HPPAC will present research that reduces (1) power consumption, (2) energy consumption, or (3) heat generation with little or no performance penalty in high-performance computing systems. In effect, the workshop aims to move towards "greener" solutions for datacenters and supercomputing centers. Examples include Green Destiny (2001), The Green Grid (2007), The Green500 List (2007), and the INRIA Green-Net Initiative (2008).

Submission Guidelines

All papers should not exceed 8 single-spaced, double column pages (US Letter) in 10pt font. All papers will be reviewed. Accepted papers will appear in the printed program book and CD-ROM proceedings of the main conference, IPDPS2012. Click here to submit a paper.

Program

9.00-10.00 Keynote (Chair: Bronis R. de Supinski)
Towards Green-HPC : (some) challenges, approaches and expectations
Laurent Lefevre (INRIA) - BIO

Energy has recently become one of the main limiting factor for designing large scale distributed systems. This talk will overview some current approaches for designing energy efficient systems (coming from recent activities in GreenTouch, PrimeEnergyIT, CompatibleOne and XLCloud projects). Some focus will be proposed on energy efficiency in virtualized environments and on Green Exascale services.

10.00-10.30 Coffee break
10.30-12.00Session 1 (Chair: Laurent Lefevre): Capping and Scheduling
Beyond DVFS: A First Look at Performance Under a Hardware-Enforced Power Bound
Barry Rountree; Dong Ahn; Bronis R. de Supinski; David Lowenthal; Martin Schulz
A Power Provision and Capping Architecture for Large Scale Systems
Yongpeng Liu; Hong Zhu; Kai Lu; Yongyan Liu
Dynamic Thread Scheduling in Asymmetric Multicores to Maximize Performance-per-Watt
Arunachalam Annamalai; Rance Rodrigues; Israel Koren; Sandip Kundu
12.00-1.30 Lunch
1.30-3.00Session 2 (Chair: Bronis R. de Supinski): Power and Energy Profiling and Metrics
The Green Index: A Metric for Evaluating System-Wide Energy Efficiency in HPC System
Balaji Subramaniam; Wu-chun Feng
Energy Efficiency Analysis of GPUs
Juan M. Cebrián; Ginés D. Guerrero; José M. García
Tracing and Visualization of Energy-Related Metrics
Timo Minartz
3.00-3.30 Coffee break
3.30-4.30Session 3 (Chair: Thomas R.W. Scogland ): Energy Workloads
Modeling Power and Energy Usage of HPC Kernels
Ananta N Tiwari; Michael Laurenzano; Laura Carrington; Allan Snavely
Power-Efficient Schemes Via Workload Characterization on the Intel's Single-chip Cloud Computer
Gustavo Chaparro-Baquero; Qi Zhou; Chen Liu; Jie Tang; Shaoshan Liu
4.30-5.30Session 4 (Chair: Thomas R.W. Scogland): Power Efficient Hardware
Energy-Efficient, Fault-Tolerant Unified Buffer and Bufferless Crossbar Architecture for NoCs
Yixuan Zhang; Randy Morris, Jr.; Dominic DiTomaso; Avinash Kodi
Optimizing Data Allocation and Memory Configuration for Non-Volatile Memory-Based Hybrid SPM on Embedded CMPs
Jingtong Hu; Qinfeng Zhuge; Chun Xue; Wei-Che Tseng; Edwin Sha
5.30-5.35Closing
Topics

  • Novel power-aware architectures for HPC
  • Power-aware middleware for HPC
  • Power-aware runtime systems for HPC
  • Reduced power/energy/heat algorithms & applications
  • Surveys or studies of power/energy/heat usage of HPC applications and systems

Workshop Co-Chairs

  • Bronis R. de Supinski, Lawrence Livermore National Laboratory, USA

  • Roberto Gioiosa, Barcelona Supercomputing Center, Spain

Publicity chairs

  • Yunquan Zhang, Chinese Academy of Sciences, China

Program Committee

  • Frank Bellosa, University of Karlsruhe
  • Taisuke Boku, University of Tsukuba
  • Laura Carrington, San Diego Supercomputer Center
  • Yuan Chen, HP Labs
  • Marco Cesati, University of Rome "Tor Vergata"
  • Wuchun Feng, Virginia Tech
  • Canturk Isci, IBM
  • Rong Ge, Marquette University
  • Rob Knauerhase, Intel Labs
  • Laurent Lefevre, INRIA and University of Lyon
  • Dong Li, Oak Ridge National Laboratory
  • David Lowenthal, University of Arizona
  • Naoya Maruyama, Tokyo Institute of Technology
  • Sally A. McKee, Chalmers Univesrity
  • Tali Moreshet, Swarthmore College
  • Hiroshi Nakashima, Kyoto University
  • Ripal Nathuji, Microsoft
  • Suzanne Rivoire, Sonoma State University